This invention relates to programmable logic devices, such as field programmable gate arrays (FPGA), and more specifically, to interface blocks of a programmable logic device to a bus or network and methods of controlling their access to the bus.
Programmable logic devices (PLDs) are a type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable resources, which may include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), transceivers, and so forth.
Each programmable resource typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic may implement the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells of the configuration memory then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices, the functionality of the device may be understood to be controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs may be programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs may be known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” may thus include but are not necessarily limited to these exemplary devices, as well as encompassing devices that may be only partially programmable.
As the density and complexity of PLDs has increased, so too has the need for greater capacity and more efficient communication circuits such as those associated with interfacing buses and/or network-on-chip. In the case of networking solutions, the increase in the number of peers or bus masters that may be associated with a bus may call for finer and/or more granular control of their access to the bus.
For circuits of a PLD directed to a bus or network-on-chip therefore, it may be desirable for at least some of the programmable resources of the PLD to be dedicated to controlling when a bus master of a plurality may inject data onto a given bus or network.